Semiconductors are materials whose ability to conduct electricity falls between that of a metal and an insulator, and that tunable conductivity is what makes nearly every modern electronic device possible. Silicon is the workhorse, but the semiconductor family includes compounds like gallium arsenide, silicon carbide, and gallium nitride, each suited to different jobs. Understanding how these materials are grown, shaped into transistors, and assembled into chips reveals a manufacturing chain of staggering complexity, one that consumes enormous resources and sits at the center of global economic competition.
What Makes a Semiconductor a Semiconductor
Metals conduct electricity freely because their electrons move with little resistance. Insulators do the opposite. Semiconductors sit in between thanks to an energy gap, commonly called the band gap, that separates electrons bound to atoms from electrons free to carry current. At absolute zero, a pure semiconductor behaves like an insulator. Add a little heat, light, or the right chemical impurity and some electrons gain enough energy to jump across that gap, allowing current to flow in a controlled way.
The size of the band gap determines a semiconductor’s personality. Silicon’s gap is about 1.1 electron volts, which works well for everyday electronics. Materials with wider gaps, above roughly 3 electron volts, handle higher voltages and temperatures before breaking down. That distinction matters enormously for applications like electric-vehicle power systems and high-frequency communications, where silicon reaches its limits.
Doping and the Two Flavors of Conductivity
Pure silicon is not very useful on its own. What makes it powerful is doping: intentionally adding tiny amounts of other elements to shift its electrical behavior. Add an element with one extra electron in its outer shell, like phosphorus, and you get n-type silicon, where the extra electrons serve as mobile charge carriers. Add an element with one fewer electron, like boron, and you create p-type silicon, where the missing electron positions (called holes) act as positive charge carriers.
This same principle applies to newer materials. Researchers have demonstrated precise p-type and n-type doping of two-dimensional semiconductors like molybdenum ditelluride by incorporating trace amounts of niobium or rhenium into the crystal. Adding just 0.06% rhenium was enough to flip a sample from hole-conducting to electron-conducting, and increasing the dopant concentration allowed the carrier density to be tuned across several orders of magnitude.1Nature Communications. Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits The ability to control conductivity this finely is what allows billions of transistors on a single chip to switch on and off in the right sequence.
Growing the Silicon Crystal
Before any chip can be made, you need an extremely pure, defect-free silicon crystal. The dominant method for producing these is the Czochralski process, in which a small seed crystal is dipped into a crucible of molten silicon and slowly pulled upward while rotating. As it rises, silicon atoms from the melt arrange themselves onto the seed in a near-perfect single-crystal lattice, forming a large cylindrical ingot.2Journal of Crystal Growth. A first-principle model of 300 mm Czochralski single-crystal Si production process for predicting crystal radius and crystal growth rate Modern ingots can be 300 millimeters (about 12 inches) in diameter and weigh over 100 kilograms.
The ingot is then sliced into thin wafers, polished to a mirror finish, and shipped to a fabrication plant, commonly called a fab. The purity requirements are extreme: impurity levels are measured in parts per billion. Even trace contamination can ruin the electrical properties of the final chips, which is why semiconductor fabs are thousands of times cleaner than a hospital operating room.
Patterning Chips With Light
Once a polished wafer arrives at a fab, the process of turning it into functional circuits begins with photolithography. A light-sensitive coating is applied to the wafer’s surface, then ultraviolet light is shone through a mask containing the circuit pattern. Where light hits the coating, chemical changes allow the exposed (or unexposed) regions to be washed away, leaving a precise pattern that guides subsequent etching and deposition steps.
As transistors have shrunk, the wavelength of light used in lithography has had to shrink with them. The current frontier is extreme ultraviolet (EUV) lithography, which uses light with a wavelength of just 13.5 nanometers. EUV extends photolithography to produce the most advanced integrated circuits available today, though the machines that generate and focus that light are among the most complex and expensive ever built.3Nature Photonics. Lithography gets extreme A single EUV scanner costs on the order of several hundred million dollars, and only one company in the world manufactures them.
Building Up and Trimming Down at the Atomic Scale
Photolithography defines the horizontal pattern, but modern chips are three-dimensional structures with dozens of stacked layers. Building those layers requires depositing thin films of various materials and etching away the parts that are not needed, often with atomic-scale precision.
Atomic layer deposition (ALD) adds material one atomic layer at a time. Unlike older methods like physical or chemical vapor deposition, ALD is self-limiting: each cycle deposits exactly one layer and then stops, giving excellent thickness control and the ability to coat complex 3D shapes uniformly.4Micro and Nanosystems. Critical Atomic-level Processing Technologies: Remote Plasma-enhanced Atomic Layer Deposition and Atomic Layer Etching Its counterpart, atomic layer etching (ALE), removes material one layer at a time with the same precision and uniformity.
Researchers are pushing these techniques further. One approach combines plasma-enhanced ALD with quasi-ALE to achieve topographically selective deposition, meaning material can be placed only on specific surfaces of a 3D structure, such as the vertical sidewalls, without coating the top or bottom.5Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films. Topographical selective deposition: A comparison between plasma-enhanced atomic layer deposition/sputtering and plasma-enhanced atomic layer deposition/quasi-atomic layer etching approaches That kind of spatial control becomes critical when feature sizes are only a few nanometers wide and traditional methods of applying a uniform blanket film would short-circuit the device.
The Shrinking Transistor and Changing Shapes
For decades, transistors were flat structures etched into the wafer surface. As they shrank, controlling current flow through such thin, short channels became increasingly difficult because electrons could leak through even when the transistor was supposed to be off. The industry’s solution was to go three-dimensional.
The first major shift was the FinFET, where the conducting channel stands up like a fin so the gate electrode can wrap around it on three sides, giving much better control. The latest evolution is the gate-all-around (GAA) architecture, in which the gate completely surrounds the channel on all four sides. This progression from planar transistors to FinFETs to GAA designs has been a key enabler of continued scaling to smaller technology nodes.6Nano Letters. Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective Leading chipmakers began shipping GAA-based processors around 2024, and the architecture is expected to carry the industry through the next several generations of shrinking.
Measuring these structures accurately is its own engineering challenge. When features are only a few nanometers across, conventional optical microscopes cannot resolve them. Low-voltage scanning electron microscopes have become essential tools for both measuring critical dimensions and inspecting for defects at these scales.7PubMed Central. Submicrometer Microelectronics Dimensional Metrology: Scanning Electron Microscopy
Stacking Chips Instead of Shrinking Them
Making transistors smaller is not the only way to improve performance. Advanced packaging techniques let chipmakers stack multiple chips or chiplets vertically and connect them with dense arrays of tiny copper pillars or through-silicon vias (TSVs), vertical electrical pathways drilled straight through a silicon die. This approach shortens the distance data has to travel, increases bandwidth, and reduces power consumption compared to spreading everything across a single flat chip.
An early landmark came in 2011, when IBM and Micron used TSV-based 3D integration to build a hybrid memory cube that offered data bandwidth up to 128 gigabytes per second, a roughly 90% reduction in package size, and about 70% lower power consumption relative to traditional memory packaging.8ScienceDirect. Review Through-silicon via advanced packaging technology and its radio frequency applications Since then, 3D stacking has become central to high-bandwidth memory used in AI accelerators and data centers. Chiplet-based designs, where a processor is assembled from multiple smaller dies rather than one monolithic slab, are also growing rapidly because they improve manufacturing yields and allow mixing different technologies in a single package.
Wide-Bandgap Semiconductors for Power and Speed
Silicon handles the vast majority of computing tasks, but it struggles in situations that demand high voltages, high temperatures, or very fast switching. That is where wide-bandgap semiconductors come in. Materials like silicon carbide (SiC) and gallium nitride (GaN) have band gaps above 3 electron volts, which gives them higher breakdown voltages, better thermal conductivity, and the ability to switch faster with lower energy losses compared to silicon.9Intell. Sustain. Manuf. Wide-Bandgap Semiconductors: A Critical Analysis of GaN, SiC, AlGaN, Diamond, and Ga2O3 Synthesis Methods, Challenges, and Prospective Technological Innovations
You encounter these materials more often than you might think. GaN is already common in compact laptop chargers and phone adapters because its fast switching enables smaller transformers. SiC inverters are used in electric vehicles to convert battery power into the alternating current that drives the motor, squeezing more range out of every kilowatt-hour. And both materials appear in 5G base stations, where their ability to handle high frequencies and high power simultaneously is difficult to match with silicon alone.
The tradeoff is cost. Growing large, defect-free SiC or GaN crystals is harder and more expensive than growing silicon. SiC wafers, for instance, are still typically limited to 150 or 200 millimeters in diameter, compared to 300 millimeters for silicon. Researchers are also exploring even wider-gap materials like gallium oxide and diamond, though these are still largely in the laboratory stage.
Two-Dimensional Semiconductors and the Scaling Frontier
As transistor channels shrink below a few nanometers, silicon starts to misbehave. Electrons scatter off surfaces and interfaces more easily in a thin silicon channel, degrading performance. Two-dimensional semiconductors, materials that are naturally just one or a few atoms thick, offer a potential way around this problem because their atomic thinness is a feature rather than a manufacturing challenge.
Molybdenum disulfide (MoS₂) is the most studied example. Researchers and industry groups have recognized 2D semiconductors as a promising solution for future technology nodes where quantum-confinement effects limit silicon, and over the past decade the key issues around material quality, processing, and integration have been addressed one by one.10PubMed Central. Modifying the Power and Performance of 2-Dimensional MoS2 Field Effect Transistors Performance projections suggest that if the remaining obstacles around electrical contacts, gate insulator scaling, and carrier mobility can be solved, MoS₂ transistors could significantly outperform silicon GAA transistors at the most advanced nodes.11Scientific Reports. Impact of device scaling on the electrical properties of MoS2 field-effect transistors
Those “ifs” are substantial, though. Growing uniform, wafer-scale films of 2D materials without defects is still difficult. Making reliable, low-resistance electrical contacts to a sheet of atoms is a different kind of engineering problem than anything silicon fabrication has faced. The consensus in the field is that 2D semiconductors are a real contender for chips a decade or more from now, not a drop-in replacement for silicon today.
Teaching Silicon to Glow
One of silicon’s biggest limitations has nothing to do with electronics. Silicon is terrible at emitting light. Its band gap is “indirect,” meaning that when electrons release energy, most of it goes into vibrations in the crystal lattice rather than into photons. That is why the lasers, LEDs, and photodetectors used in fiber-optic communications and displays are made from other materials, typically gallium arsenide or indium phosphide.
A breakthrough in recent years has been the development of hexagonal silicon-germanium alloys. Ordinary silicon and germanium crystallize in a cubic diamond structure, but when coaxed into a hexagonal crystal structure, silicon-germanium alloys with high germanium content (above about 65%) exhibit a direct band gap. Researchers have demonstrated direct-bandgap quantum wells in this material system with the type of band alignment needed for light-emitting devices.12PubMed Central. Direct bandgap quantum wells in hexagonal Silicon Germanium If this work matures, it could eventually allow light sources and electronic circuits to be built on the same silicon-compatible platform, a long-standing goal in the chip industry that would simplify photonic integration enormously.
The Environmental Cost of Making Chips
Semiconductor fabrication is resource-intensive in ways that often surprise people. The ultra-clean water, high-purity chemicals, and energy-hungry tools required at every step add up. In 2021, the global semiconductor industry’s total water withdrawal reached roughly 789 million cubic meters, total energy consumption hit about 149 billion kilowatt-hours, and total greenhouse gas emissions were around 71.5 million metric tons of CO₂ equivalent.13Water Cycle. Environmental data and facts in the semiconductor manufacturing industry: An unexpected high water and energy consumption situation
A huge fraction of that water goes to producing ultrapure water (UPW), which is needed for rinsing wafers between process steps. UPW must be free of virtually all dissolved minerals, organic molecules, and particles, so ordinary tap water goes through extensive filtration, deionization, and UV treatment before it is clean enough for the fab. Worldwide UPW consumption was estimated at about 551 million cubic meters in 2021.14Water Cycle. Environmental data and facts in the semiconductor manufacturing industry: An unexpected high water and energy consumption situation Leading chipmakers have set targets to recycle and reuse more of this water, but as fabrication processes grow more complex and production volumes climb, total consumption continues to rise.
Energy use is similarly stubborn. EUV lithography tools alone can draw hundreds of kilowatts during operation, and a modern fab may run around the clock. The industry’s greenhouse gas footprint also includes potent process gases like nitrogen trifluoride and sulfur hexafluoride, which are used in etching and chamber cleaning and have global warming potentials thousands of times greater than CO₂ on a per-molecule basis.
Supply Chain Geography and Geopolitical Friction
The semiconductor supply chain is one of the most geographically concentrated and interdependent in any industry. Design, raw materials, equipment manufacturing, wafer fabrication, and assembly and testing each cluster in different regions. The most advanced chip fabrication is dominated by a handful of companies in East Asia, while the critical lithography equipment comes from a single supplier in the Netherlands, and many specialty chemicals and gases originate from specific plants in Japan or Europe.
This concentration has turned into a geopolitical flashpoint. Sanctions, export controls, and critical-mineral dependencies have converted what were already known chokepoints into systemic vulnerabilities. In response, companies are not simply decoupling from risky suppliers but pursuing a combination of strategies: relocating manufacturing capacity through reshoring and nearshoring, diversifying their supplier base with pre-approved alternates at every tier, and investing in digital risk monitoring tools like predictive analytics and control-tower supply-chain visibility.15Journal of Emerging Business Innovation Management. Impact of Geopolitical Risks on Global Supply Chain Strategies: Evidence from the Semiconductor Industry These measures raise resilience but come with real costs: new fabs take years to build, skilled workers are scarce, and duplicating supply chains is expensive.
Governments worldwide have responded with large subsidy programs. The United States passed the CHIPS and Science Act in 2022, the European Union has its own European Chips Act, and Japan, South Korea, and India have all launched incentive packages aimed at attracting fab construction. Whether these investments will meaningfully diversify the supply chain or simply shift the bottlenecks remains an open question; building the physical fab is only one piece, and the surrounding ecosystem of specialized suppliers, technicians, and institutional knowledge is harder to transplant.
Memristors and Neuromorphic Computing
Conventional computers shuttle data back and forth between a processor and separate memory, a bottleneck that wastes time and energy. A growing body of research is exploring devices that blur the line between computing and memory, potentially doing both in the same physical location. The most prominent candidate is the memristor, a component whose electrical resistance changes depending on how much current has previously flowed through it, effectively giving it a form of memory.
Memristors are being investigated as a path to power-efficient in-memory computing, deep-learning accelerators, and spiking neural networks that more closely mimic how biological brains process information.16Advanced Intelligent Systems. Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing In one demonstration, a 1,000-element memristor array was trained in situ to perform sound localization, a task brains handle effortlessly but traditional chips find cumbersome. Using a multi-threshold training scheme, the researchers reduced prediction error by about 46% compared to a conventional programming approach.17Nature Communications. Memristor-based analogue computing for brain-inspired sound localization with in situ training
Memristive hardware is still far from competing with established silicon logic for general-purpose tasks. Variability between individual devices, endurance limitations after many write cycles, and the difficulty of integrating memristors into existing manufacturing flows are active research problems. But for specific workloads where massive parallelism and low power matter more than raw clock speed, particularly inference tasks in artificial intelligence, memristors represent one of the more tangible “beyond-silicon” computing ideas under development.
Why One Material Will Never Be Enough
A recurring theme across the semiconductor landscape is specialization. Silicon dominates general-purpose computing and will for the foreseeable future, but it shares the stage with a growing roster of materials tuned for specific jobs. GaN and SiC handle power conversion and radio-frequency amplification. Indium phosphide and gallium arsenide underpin fiber-optic communications. Hexagonal silicon-germanium may one day bring light emission into the silicon family. Two-dimensional materials like MoS₂ could extend transistor scaling when silicon channels become too thin to function well.
This material diversity complicates manufacturing because each compound has its own crystal-growth challenges, processing quirks, and defect profiles. It also creates economic pressure: fabs built for one material cannot easily be retooled for another, so the investment decisions made today lock in capabilities for a decade or more. For anyone watching the industry, the important thing to understand is that “semiconductor” is not a synonym for “silicon.” It is a broad class of materials, and the future of electronics depends on choosing the right one for each application rather than searching for a single universal replacement.