3D NAND is a type of flash memory that stacks storage cells vertically in dozens or hundreds of layers, rather than spreading them across a flat surface. It’s the technology inside virtually every modern SSD, USB drive, and smartphone. By building upward instead of outward, manufacturers can pack far more storage into the same physical space while improving reliability and speed compared to older, flat (2D or “planar”) NAND designs.
How 3D NAND Differs From Flat NAND
Traditional NAND flash stores data in a single layer of memory cells arranged on a flat chip. For years, manufacturers made storage denser by shrinking each cell smaller and smaller. But by the mid-2010s, cells had gotten so tiny that they started interfering with each other electrically, causing data errors and shorter lifespans.
3D NAND solves this by stacking layers of cells vertically, like floors in a high-rise building. Instead of shrinking cells to dangerous dimensions, each cell can actually be slightly larger than in planar NAND, which makes it more reliable. The density gains come from height, not miniaturization. Early 3D NAND chips had 24 or 32 layers. Today, Samsung’s latest generation reaches 290 layers, and the company has a 430-layer design in development. Every major manufacturer is targeting 1,000-layer 3D NAND by 2030.
How Data Gets Stored in Each Cell
Every memory cell in a NAND chip stores data by trapping electrical charge. There are two main approaches to this. Floating-gate cells trap electrons on a small conductive island surrounded by insulation. Charge-trap cells instead store electrons directly in an insulating layer, which is simpler to manufacture at high layer counts. Most 3D NAND today uses charge-trap technology, though some manufacturers still produce floating-gate 3D designs.
The amount of data each cell holds depends on how many voltage levels it can distinguish:
- SLC (Single-Level Cell) stores 1 bit per cell. It’s the fastest and most durable, lasting around 100,000 write-erase cycles, but it’s expensive and mainly used in high-performance enterprise applications.
- MLC (Multi-Level Cell) stores 2 bits per cell, with roughly 10,000 write-erase cycles.
- TLC (Triple-Level Cell) stores 3 bits per cell at about 3,000 write-erase cycles. This is the most common type in consumer SSDs today, balancing cost, capacity, and lifespan.
- QLC (Quad-Level Cell) stores 4 bits per cell. It offers the highest density and lowest cost but has the fewest write-erase cycles, making it best suited for read-heavy workloads.
The shift to 3D stacking has helped offset the endurance penalty that comes with packing more bits per cell. A 3D TLC cell is generally more reliable than a 2D TLC cell of the same generation because the larger cell geometry reduces electrical interference between neighboring cells.
Why Stacking Hundreds of Layers Is Difficult
Building a 3D NAND chip means drilling billions of tiny vertical holes through a tall stack of alternating material layers, then filling those holes precisely to create functional memory cells. These channel holes have extreme aspect ratios, meaning they’re incredibly deep relative to their width. As layer counts climb past 200 and toward 300, keeping each hole perfectly straight from top to bottom without distortion or twisting becomes the central engineering challenge.
Manufacturers also need to place the chip’s control logic somewhere. A technique called CMOS-under-Array tucks the processing circuitry beneath the memory stack itself, so the logic doesn’t eat into the chip’s footprint. This improves storage density per square millimeter and is now standard practice across the industry.
What 3D NAND Means for SSD Prices
For most of the last decade, 3D NAND drove SSD prices steadily downward. More layers meant more gigabytes per wafer, which meant cheaper storage. A 1 TB SSD that cost several hundred dollars in 2015 dropped below $100 at various points.
That trend has recently reversed. NAND flash wafer costs have climbed sharply, with 1 Tb TLC wafer prices roughly tripling since late 2025 and some configurations rising nearly fivefold. The main driver is that chipmakers have been redirecting production capacity toward enterprise SSDs, where profit margins are higher, leaving less supply for consumer products. The surge in demand from AI infrastructure has intensified this crunch. At current pricing, SSDs cost roughly 16 times more per gigabyte than traditional hard drives.
These price swings are cyclical in the memory industry, and the long-term trajectory still favors denser, cheaper storage as layer counts increase. But in the short term, buyers should expect higher prices than the historic lows of recent years.
SLC, TLC, QLC: Which Type Is in Your SSD
If you’re buying a consumer SSD in 2025, it almost certainly uses 3D TLC NAND. TLC hits the sweet spot for everyday computing: enough write endurance to last years under normal use, good read and write speeds, and reasonable pricing. Most mainstream drives from Samsung, Western Digital, SK Hynix, and Micron are TLC-based.
QLC drives are increasingly common in budget and high-capacity models. They’re a fine choice if your workload is mostly reading data (gaming libraries, media storage, general web browsing) rather than constantly writing large files. The lower endurance of QLC rarely matters for typical consumer use, since even 3,000 write-erase cycles translates to hundreds of terabytes of total writes over a drive’s lifetime when combined with the SSD controller’s wear-leveling algorithms.
SLC and MLC are largely confined to enterprise and industrial applications where maximum endurance or consistent low latency justifies the higher cost.
What Comes Next: More Layers and More Bits
The industry roadmap has two parallel tracks: stacking more layers and squeezing more bits into each cell.
On the stacking front, every major manufacturer is racing toward 1,000 layers by 2030. Samsung’s progression from 236 layers to 290, with 430 planned next, illustrates the pace. Each generation jump requires advances in the etching and deposition processes that form those ultra-deep channel holes.
On the bits-per-cell front, PLC (Penta-Level Cell) technology would store 5 bits per cell, a step beyond QLC. It hasn’t reached commercial production yet because distinguishing 32 voltage levels in a single cell creates serious reliability and read-speed problems. SK Hynix presented a novel approach at the 2025 IEDM conference that splits each cell into two independent storage sites, each handling only six voltage states. Combining the two sites yields 36 possible states, more than the 32 needed for 5-bit storage, with a few spare states that act as an error buffer. The company claims this delivers read speeds up to 20 times faster than conventional PLC approaches. It’s still a research-stage technology, but it signals a plausible path to even denser, cheaper storage in the years ahead.