A chiplet is a small, self-contained piece of silicon designed to be combined with other chiplets inside a single chip package, rather than having every function built onto one large slab of silicon. The idea is straightforward: instead of making one enormous, do-everything chip (called a monolithic design), you break the design into smaller functional blocks, manufacture each one separately, and then wire them together in advanced packaging. This approach has become the dominant strategy for building high-performance processors, and it is reshaping everything from manufacturing economics to geopolitics.
Why the Industry Stopped Making One Big Chip
For decades, chipmakers followed a simple playbook: cram more transistors onto a single piece of silicon by shrinking them. That worked beautifully until the chips themselves started getting physically enormous. A modern high-performance processor might need a die area of 600 or 800 square millimeters to fit all the transistors it needs. The problem is that silicon wafers are not perfect. Tiny defects are scattered randomly across every wafer, and the larger a chip is, the more likely it is to overlap with one of those defects and fail. A chip twice as large does not just cost twice as much to make; it can cost far more, because the fraction of working chips (the yield) drops sharply as the die grows.
Chiplets sidestep this problem. By splitting a large design into several smaller dies, each individual piece has a much better chance of being defect-free. You throw away fewer bad chips, so your effective manufacturing cost goes down. Modeling work has shown that re-partitioning a monolithic system-on-chip into several chiplets can save up to roughly half of the die cost, with especially strong advantages at the most advanced manufacturing nodes like 5 nanometers, where defects account for over half of the total manufacturing cost of a large monolithic chip.1arXiv. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration The savings are less dramatic at more mature process nodes where yields are already high, but at the cutting edge, chiplets are an economic lifeline.
How Chiplets Get Wired Together
Splitting a chip into pieces only works if you can reconnect those pieces with fast, reliable communication links. This is where advanced packaging comes in. The most common approach for high-performance designs is a 2.5D architecture, which places multiple chiplets side by side on a shared silicon interposer, a thin layer of silicon that acts as a high-density circuit board beneath the chiplets. Wires connecting different chiplets are routed through the interposer, and the interposer itself connects to the package substrate below via vertical pathways called through-silicon vias, exposing pins to memory and other external hardware.2ACM Digital Library. The Survey of Chiplet-based Integrated Architecture: An EDA perspective – Section: 2 Architecture Design of Chiplet
The 2.5D layout provides high-bandwidth communication between chiplets through the interposer, which reduces latency and improves data transfer compared to routing signals off-chip entirely. It also allows different chiplets to be made using different manufacturing processes. A high-performance compute core might be built on an expensive, bleeding-edge 3-nanometer node, while a less demanding I/O controller chiplet can be manufactured on a cheaper, older node. This mix-and-match capability is one of the core economic and engineering advantages of the chiplet approach.3ACM Digital Library. The Survey of Chiplet-based Integrated Architecture: An EDA perspective – Section: 2 Architecture Design of Chiplet
Beyond 2.5D, there are also 3D architectures that stack chiplets vertically, one on top of another, connected by very short vertical links. This shrinks the distance signals need to travel and packs more functionality into a smaller footprint. But stacking introduces its own headaches, particularly around heat, since the inner layers have no direct path to a heatsink.
The Universal Chiplet Interconnect Standard
If chiplets from different manufacturers are ever going to work together seamlessly, they need a common language. That is the goal of the Universal Chiplet Interconnect Express, or UCIe, an industry standard defining how chiplets talk to each other at the physical and electrical level. Getting UCIe to work in practice means designing the tiny physical connections, the silicon bridges and bump arrays, that carry signals between chiplets at very high speeds.
Recent work on embedded silicon bridges for 2.5D packages has demonstrated that these interconnects can achieve excellent signal integrity at 32 gigabits per second, with bump pitches as small as 45 micrometers, meeting the UCIe specifications for advanced packaging.4Microelectronics Reliability. Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe) Those numbers matter because the closer together you can place the connection bumps and the faster they can transmit, the more bandwidth you can squeeze between chiplets without blowing your power budget. If UCIe succeeds as an open standard, it could eventually allow companies to buy chiplets from different vendors and assemble them into custom products, much as you can plug different components into a PC motherboard today. That vision is still aspirational, but the physical building blocks are being validated.
The Packaging Cost Trade-off
Chiplets save money on silicon, but they add cost in packaging. Interposers, silicon bridges, and the precise assembly process needed to align chiplets and their thousands of tiny connections are not cheap. Cost modeling shows that when you factor in this packaging overhead, the net savings from chiplets shrink, and in some configurations, the advantage can be modest. For a system with a relatively small number of cores, packaging costs can account for around 30% of the total.5arXiv. Chiplet Actuary: A Quantitative Cost Model and Multi-Chiplet Architecture Exploration
The sweet spot for chiplets, economically, depends on the manufacturing node and the total chip area. At the most advanced nodes, where wafer costs are high and defect-related losses are severe, the yield gains from smaller dies easily justify the packaging expense. But as a given process node matures and yields improve, the balance tips. A chiplet design that made overwhelming economic sense in the first year of a new node might look only marginally better than a monolithic chip two years later when yields have climbed. This is part of why the economic case for chiplets is strongest at the bleeding edge and weaker for mid-range products that do not need the latest process technology.
Heat, Power, and the Physics of Packing Chips Close Together
Putting multiple high-power chiplets onto a single interposer concentrates a lot of heat into a small area. The rapid increase in packaging density and power density of 2.5D interposers presents significant challenges for thermal management.6Thermal Science and Engineering Progress. High-efficient and fast-response thermal management by heterogeneous integration of diamond on interposer-based 2.5D chiplets In a monolithic chip, heat spreads laterally across a large, continuous piece of silicon. In a multi-chiplet package, each chiplet is a separate thermal island, and the interfaces between chiplets and the interposer can act as thermal bottlenecks. Researchers are exploring exotic solutions, including integrating diamond, an exceptional thermal conductor, into interposer structures to help move heat away from hot spots more quickly.
Delivering clean, stable power to chiplets is equally tricky. The power delivery network has to traverse the interposer and reach each chiplet through those same fine-pitched connections used for signals. Research into co-optimizing the power delivery networks of both the chiplets and the interposer has shown that careful design can improve voltage stability by around 27%, reducing the “IR-drop” that robs chiplets of the voltage they need.7IEEE Transactions on Components, Packaging, and Manufacturing Technology. Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs But this improvement comes with trade-offs: the same optimization that reduces voltage drop can increase total power consumption by over 11% and produce higher output ripple and initial ringing from the inductive behavior of the interposer’s power delivery grid.8IEEE Transactions on Components, Packaging, and Manufacturing Technology. Chiplet/Interposer Co-Design for Power Delivery Network Optimization in Heterogeneous 2.5-D ICs In plain terms, improving one electrical property in a multi-chiplet system can worsen others, and finding the right balance requires system-level thinking that did not exist in the monolithic chip era.
The Design Tool Gap
Building a monolithic chip is hard, but at least the electronic design automation (EDA) tools for doing it have been refined over decades. Chiplets break assumptions those tools were built around. When your design spans multiple dies, each potentially manufactured on a different process node, the software needs to handle cross-die timing, power analysis across interposer boundaries, and signal integrity through packaging interconnects that behave differently from on-chip wires. These are not just incremental extensions to existing tools; they require fundamentally new modeling and analysis capabilities.
Today, designers often piece together workflows from tools that were not originally designed to talk to each other. The chiplet sitting on the interposer might be designed in one tool, the interposer layout in another, and the package-level signal integrity analysis in a third. Integrating these flows is one of the less glamorous but very real bottlenecks slowing chiplet adoption, especially for smaller companies that lack the engineering resources to build custom internal tool chains. Industry groups working on UCIe and related standards are trying to address some of this by specifying standardized interface models, but a truly unified design environment for chiplet-based systems remains a work in progress.
Testing Before You Assemble
A subtle but expensive problem with chiplets is testing. When you build a monolithic chip, you test it once, at the end of the manufacturing line, and either ship it or toss it. When you assemble multiple chiplets into a package, you ideally want to know that each chiplet works before you bond it down, because once it is attached, reworking a failed chiplet is difficult and sometimes impossible. The industry calls a chiplet that has passed testing a “known good die,” or KGD.
Achieving KGD status is harder than it sounds. The fine-pitched bumps on a chiplet, sometimes 45 micrometers apart, are tiny, and probing them for electrical testing without damaging them is a delicate operation. If even one bad chiplet gets assembled into a multi-chiplet package, it can turn the entire expensive package into scrap. This drives up both testing costs and the economic stakes of test escapes. The industry is investing heavily in new probing and test technologies to address this, including approaches that use temporary, reworkable connections to test chiplets before permanent assembly.
Supply Chain Vulnerabilities
Chiplets introduce a supply chain complexity that monolithic chips do not have. A single monolithic chip might go through one fabrication facility and one packaging house. A chiplet-based product might involve chiplets fabricated at different foundries, on different continents, all converging at an advanced packaging facility for assembly. Each handoff is a potential point of failure, delay, or security concern.
Most of the world’s outsourced semiconductor assembly and test facilities are located offshore from the United States, primarily in East and Southeast Asia. Research into the advanced packaging supply chain has raised concerns about possible bottlenecks and security vulnerabilities associated with this geographic concentration.9arXiv. US Microelectronics Packaging Ecosystem: Challenges and Opportunities If chiplets from a sensitive application, say a military processor, are assembled at a facility outside national jurisdiction, there are concerns about tampering, counterfeiting, or supply disruption. These worries are not hypothetical; they are a primary driver of policy efforts to bring advanced packaging capabilities onshore.
The security dimension goes beyond just geography. When chiplets from multiple sources are integrated into one package, verifying the authenticity and integrity of each component becomes harder. A chiplet that looks electrically correct in testing might still contain subtle modifications. Research into authentication frameworks for multi-chiplet systems is an active area, aiming to create cryptographic methods that can verify each chiplet’s identity and provenance after assembly.
The CHIPS Act and the Scramble for Packaging Capacity
The United States CHIPS and Science Act, signed into law in 2022, is widely known for its incentives to build new chip fabrication plants on U.S. soil. Less widely appreciated is that the legislation also authorizes, though does not require, funds to be directed toward advanced packaging projects.10Center for Security and Emerging Technology. Re-Shoring Advanced Semiconductor Packaging Policy analysts have argued that the U.S. should use these funds to incentivize domestic advanced packaging and should favor fabrication project proposals that include co-located packaging facilities, so that chips do not have to be shipped overseas for the final assembly step.11Center for Security and Emerging Technology. Re-Shoring Advanced Semiconductor Packaging
This matters because advanced packaging is arguably the bottleneck for the entire chiplet revolution. You can design the most brilliant chiplet architecture in the world, but if only a handful of facilities on the planet can actually assemble it at production volumes, your design schedule is at the mercy of whoever controls those facilities. The current concentration of advanced packaging capacity in Taiwan and a few other East Asian locations makes it a strategic chokepoint. Building domestic packaging capacity is slower and less headline-grabbing than building fabs, but without it, new fabs will still depend on overseas assembly lines to turn wafers into finished chiplet-based products.
Who Is Already Using Chiplets
The most visible commercial chiplet products have come from AMD, which broke from the monolithic tradition with its EPYC server processors starting in 2017. Rather than building one massive die, AMD used multiple smaller compute dies connected through an I/O die, and the approach proved so effective that it allowed AMD to compete with and sometimes outperform much larger rivals’ monolithic designs at a fraction of the manufacturing cost. Intel followed with its own chiplet-based architectures, and Apple’s M-series Ultra chips join two dies together using a high-bandwidth interconnect.
In the data center and AI accelerator space, chiplets have become even more critical. Training large AI models demands enormous memory bandwidth and compute density, and chiplet architectures make it possible to scale these systems beyond what any single die can deliver. The trend is accelerating: as AI workloads grow and single-die scaling slows, chiplets are shifting from a clever cost optimization to a fundamental architectural necessity.
When Chiplets Are Not the Right Answer
For all their advantages, chiplets are not universally superior to monolithic designs. If your chip is small enough to yield well on its target process node, splitting it into chiplets adds packaging cost and complexity for little benefit. Many consumer-grade chips, smartphone processors, and mid-range products are still monolithic for exactly this reason. The cross-chiplet communication links, no matter how fast, also introduce latency and power overhead that do not exist when signals travel within a single piece of silicon. For latency-sensitive applications where every nanosecond counts, the penalty of crossing a chiplet boundary can matter.
There is also an organizational cost. Designing a chiplet-based system requires cross-disciplinary teams that understand silicon design, packaging, thermal management, and system integration simultaneously. Smaller companies and startups that might love the theoretical flexibility of chiplets often lack the expertise and tooling to execute on the concept. The ecosystem of reusable, off-the-shelf chiplets that you can buy and snap together remains more of a vision than a reality. Most chiplet products today are designed by a single company that controls all the pieces, which limits the modularity benefit to internal reuse rather than an open marketplace.
The physical limits are also worth keeping in mind. Stacking more chiplets or packing them more densely compounds the thermal and power delivery challenges described earlier. At some point, the packaging technology itself becomes the performance limiter, not the transistor technology inside the chiplets. Whether the industry can push packaging innovation fast enough to keep pace with the demand for more compute is one of the defining engineering questions of the next decade.