A CPLD, or complex programmable logic device, is a type of digital chip that lets engineers create custom logic circuits without designing a chip from scratch. It sits between simple programmable logic chips and the much larger, more powerful FPGAs (field-programmable gate arrays), handling small to medium digital tasks with fast, predictable timing. CPLDs are widely used as the “glue” that connects other chips on a circuit board, managing signals, decoding addresses, and keeping everything running in the right order.
How a CPLD Is Structured Inside
A CPLD is essentially several smaller programmable logic blocks grouped together on a single chip, connected by a network of internal wires. Each block resembles an older, simpler programmable chip called a PAL or PLA, but the CPLD packages many of them together with a shared routing system so they can work as one coordinated unit.
The basic building blocks are called macrocells. Each macrocell contains a set of programmable AND gates (which combine input signals), an OR gate (which merges those combinations), and a flip-flop (a tiny memory element that can store one bit of data). This combination lets each macrocell perform a piece of logic and, if needed, remember its result for the next clock cycle. A typical CPLD groups macrocells into clusters called Logic Array Blocks (LABs). In the well-known Altera MAX 7000 family, for example, each LAB holds 16 macrocells arranged in two sets of eight.
Connecting all these blocks is a Programmable Interconnect Array (PIA), sometimes called a Global Routing Pool or Central Switch Matrix depending on the manufacturer. This interconnect can route any block’s output to any other block’s input across the entire chip. Because the routing paths are fixed in length and structure, signals travel through the chip in a consistent, predictable amount of time, which is one of the CPLD’s defining advantages.
Why Timing Is Predictable
One of the main reasons engineers choose CPLDs is their deterministic timing. A signal entering a CPLD pin and exiting another pin passes through the same number of logic stages and the same interconnect structure regardless of which macrocells are used. In the Altera MAX 7000 family, a simple logic function like a half adder completes in roughly 6 nanoseconds from input to output. Even a slightly more complex function, like a two-bit ripple carry adder, clocks in around 9.5 nanoseconds.
This consistency matters in applications where signals must arrive at exact times. FPGAs, by contrast, use a more flexible routing mesh that can introduce variable delays depending on where logic ends up placed inside the chip. CPLDs avoid that unpredictability by keeping their interconnect structure fixed.
Non-Volatile Configuration
CPLDs store their programming in non-volatile memory, typically flash or EEPROM cells built into the chip. This means the logic configuration survives when power is removed. The moment you turn the board on, the CPLD is ready to work with no boot-up delay and no need for an external configuration memory chip.
This “instant-on” behavior is critical for tasks like power-up sequencing, where the CPLD itself controls the order in which other parts of a system receive power. If the chip needed time to load its own configuration first, it couldn’t reliably manage the startup of everything else. FPGAs, by contrast, typically use volatile memory (SRAM) for their configuration and need to load their design from an external flash chip every time the system powers up, a process that can take milliseconds to hundreds of milliseconds.
Logic Capacity and Limits
CPLDs are intentionally small. Current devices from Microchip (formerly Atmel) range from 32 to 128 macrocells, with higher-density parts like the ATF2500C offering around 2,500 usable gates. That’s enough for address decoding, signal routing, and control state machines, but nowhere near enough for video processing, networking stacks, or anything requiring thousands of registers.
Propagation delays in these parts range from about 7.5 to 15 nanoseconds depending on the specific device and its operating voltage. Standard 5V versions tend to be faster (as low as 7.5 ns), while 3.3V versions run at the slower end around 15 ns. These speeds are more than adequate for the kinds of board-level control tasks CPLDs handle.
Common Uses
CPLDs show up in designs where you need a modest amount of custom digital logic that works instantly and predictably. The most common applications include:
- Glue logic: Connecting chips that weren’t designed to talk directly to each other, handling level shifting, signal gating, and protocol translation between components on a board.
- Address decoding and chip select generation: Determining which memory chip or peripheral should respond when a processor puts an address on the bus.
- Power-up sequencing: Controlling the order and timing in which voltage regulators enable, ensuring sensitive components receive power in a safe sequence.
- Bus arbitration: Managing which device gets to drive a shared data bus at any given moment, preventing signal collisions.
- I/O expansion: Adding extra input/output pins or consolidating several simple logic functions that would otherwise require a handful of discrete chips.
In all these roles, the CPLD replaces what might otherwise be a small handful of fixed-function logic chips (AND gates, OR gates, decoders, flip-flops) with a single reprogrammable device. This saves board space, reduces part count, and lets engineers fix logic bugs by reprogramming rather than redesigning the circuit board.
CPLD vs. FPGA
The most common point of confusion is how a CPLD differs from an FPGA, since both are programmable logic chips. The differences come down to size, architecture, and behavior.
FPGAs offer far more logic capacity, often containing hundreds of thousands or millions of logic elements along with dedicated memory blocks and signal processing hardware. CPLDs top out at a few hundred macrocells. If your design needs to implement a complex digital system like an image processor or a custom communication protocol, you need an FPGA. If you need to decode a few address lines and sequence some control signals, a CPLD is the right fit.
Architecturally, CPLDs use a wide AND-OR structure inherited from older PAL chips, which is naturally suited to combinational logic (outputs determined directly by input combinations). FPGAs use a lookup-table architecture that’s more flexible but introduces routing-dependent timing variation. This is why CPLDs provide consistent, predictable delays while FPGAs require careful timing analysis after the design is placed and routed.
The non-volatile advantage also matters. CPLDs power up ready. FPGAs need to load their configuration, which means they can’t reliably control anything that happens in the first moments after power is applied, unless a CPLD or other instant-on device manages that process for them.
How CPLDs Are Programmed
Designs for CPLDs are written in hardware description languages, primarily VHDL or Verilog. These are the same languages used for FPGA and custom chip design, so skills transfer directly. You describe the logic behavior you want (for instance, “when these three input signals are all high, drive this output low”), and a software tool compiles that description into a configuration file.
The configuration file is then loaded into the CPLD through a programming interface, most commonly JTAG (a standard debug and programming port found on nearly all programmable logic devices). Because the configuration is stored in non-volatile memory on the chip itself, programming only needs to happen once unless you want to change the design. Updates can be made in the field without removing the chip from the board, and some setups allow reprogramming without powering down the entire system.
Manufacturer-provided software handles the compilation, fitting (assigning your logic to specific macrocells), and timing analysis. For Microchip’s ATF family, the toolchain is relatively simple compared to FPGA workflows, reflecting the smaller scale and lower complexity of typical CPLD designs.