A full adder is a fundamental digital circuit that adds three single-bit binary inputs and produces two outputs: a sum bit and a carry-out bit. Those three inputs are two data bits (A and B) plus a carry-in bit from a previous addition. This carry-in is what separates a full adder from a simpler half adder, and it’s the reason full adders can be chained together to add numbers of any size inside processors, calculators, and virtually every piece of digital hardware that does math.
How a Full Adder Works
Binary addition follows the same logic as decimal addition, just with only two digits: 0 and 1. When you add 1 + 1 in binary, you get 0 with a carry of 1 (the same way 5 + 5 gives you 0 with a carry of 1 in decimal). A full adder handles this process for a single column of bits, including any carry coming in from the column to its right.
The circuit takes three inputs. A and B are the two bits being added, and C-in is the carry bit from a previous stage. From these, it calculates two outputs. The sum output (S) is 1 when an odd number of the three inputs are 1. The carry-out (C-out) is 1 whenever two or more of the three inputs are 1. Here’s the complete truth table:
- A=0, B=0, C-in=0 → Sum=0, C-out=0
- A=0, B=0, C-in=1 → Sum=1, C-out=0
- A=0, B=1, C-in=0 → Sum=1, C-out=0
- A=0, B=1, C-in=1 → Sum=0, C-out=1
- A=1, B=0, C-in=0 → Sum=1, C-out=0
- A=1, B=0, C-in=1 → Sum=0, C-out=1
- A=1, B=1, C-in=0 → Sum=0, C-out=1
- A=1, B=1, C-in=1 → Sum=1, C-out=1
The Logic Behind Sum and Carry
The sum output uses an operation called XOR (exclusive OR), which outputs 1 when its inputs differ. The full expression is: S = A XOR B XOR C-in. In plain terms, XOR the first two bits together, then XOR that result with the carry-in. If an odd number of the three inputs are 1, the sum is 1. If an even number (including zero) are 1, the sum is 0.
The carry-out expression is: C-out = (A AND B) OR (C-in AND (A XOR B)). This captures the two situations that produce a carry. Either both A and B are 1 (so their addition alone generates a carry), or exactly one of A and B is 1 and the carry-in is also 1, which pushes the total to 2 or more, requiring a carry to the next column.
Inside the Circuit: Gates and Half Adders
A full adder is built from five logic gates: 2 XOR gates, 2 AND gates, and 1 OR gate. That maps neatly onto two half adders plus one OR gate. A half adder only handles two inputs (no carry-in), so it’s simpler: one XOR gate and one AND gate.
The first half adder takes A and B. Its XOR gate produces A XOR B (a partial sum), and its AND gate produces A AND B (a partial carry). The second half adder takes that partial sum and the carry-in. Its XOR gate produces the final sum, and its AND gate catches the case where the partial sum and carry-in are both 1. Finally, the OR gate combines the two partial carries into the final carry-out. In standard CMOS manufacturing, this entire circuit uses 28 transistors, though optimized designs have reduced that to as few as 18.
Why the Carry-In Matters
A half adder can add two bits, but it has no way to accept a carry from a previous column. That makes it useless for anything beyond single-bit addition. Think of adding two 8-bit numbers by hand in binary: when a column produces a carry, the next column to the left needs to include it. The carry-in input on a full adder is specifically designed for this. It’s what allows full adders to be connected in sequence, with each stage’s carry-out feeding into the next stage’s carry-in.
Chaining Full Adders for Multi-Bit Addition
To add two 8-bit numbers, you line up eight full adders side by side. The carry-in of the first (least significant) adder is set to 0. Its carry-out feeds into the carry-in of the second adder, whose carry-out feeds into the third, and so on. This configuration is called a ripple carry adder, because the carry signal ripples through the chain from right to left, one stage at a time.
Ripple carry adders are simple to build, but they have a speed problem. Each full adder can’t finalize its output until it receives the carry from the previous stage. The total delay for an N-bit ripple carry adder is N times the delay of a single full adder. For a 4-bit adder where each stage takes about 4 to 5 nanoseconds for the carry path, the final result isn’t ready until the carry has passed through all four stages. Scale that to a 32-bit processor and the normalized carry chain delay reaches 131 gate delays, which is unacceptably slow for modern hardware.
Faster Alternatives to Ripple Carry
The ripple carry bottleneck drove engineers to develop smarter architectures. The most important is the carry lookahead adder (CLA). Instead of waiting for the carry to ripple through each stage sequentially, a CLA calculates all the carry signals in advance using two properties of each bit position: “generate” and “propagate.” A position generates a carry when both input bits are 1. It propagates a carry when exactly one input bit is 1, meaning an incoming carry would pass through. Since generate and propagate depend only on the input bits (not on any previous carry), they’re available almost immediately, after just one or two gate delays.
By using these terms in a set of expanded equations, a CLA can determine every carry signal in parallel rather than sequentially. A carry lookahead adder producing the sum at a given bit position might take 5 gate delays, compared to 8 gate delays for a ripple carry adder at the same position. Prefix adders push this even further, offering the fastest carry resolution at the cost of more complex hardware.
Where Full Adders Are Used
Full adders are the core building block of the arithmetic logic unit (ALU), the part of a processor that handles math and logical operations. Every time your computer adds two numbers, multiplies values, increments a counter, or calculates a memory address, full adders are doing the work at the hardware level. Multiplication circuits, for example, are largely arrays of full adders that sum partial products. Subtraction uses full adders too: the processor flips the bits of one number, sets the initial carry-in to 1 (creating a two’s complement), and adds normally.
Beyond traditional processors, full adder circuits appear in digital signal processors, graphics chips, and even experimental display technologies. Researchers have built full adder-based ALUs using thin-film transistors for flexible electronics, pointing to applications in wearable and embedded devices. At every scale of digital computing, the full adder remains the fundamental unit that turns binary logic into arithmetic.