A node in semiconductor manufacturing refers to a generation of chip technology, originally named after the smallest physical feature on a transistor. At the 90 nm node in 2003, for example, the name closely matched the actual size of key transistor features. Today, that direct link between the node name and any physical measurement has broken down. A “3 nm” chip does not contain features that are literally 3 nanometers across. Instead, the node name signals a new generation with smaller features, more transistors packed into the same space, and better performance and power efficiency than the generation before it.
How Node Names Originally Worked
In earlier decades of chipmaking, the node number corresponded to a real measurement on the chip. Two features were commonly used as the reference point: the gate length of a transistor (the tiny gap that controls whether current flows) and half the spacing between the closest metal wires on the chip’s first wiring layer, known as the Metal 1 half-pitch. At the 90 nm node, the Metal 1 half-pitch was roughly 90 nm. Each new generation shrank these dimensions by about 30%, so the industry moved from 90 nm to 65 nm to 45 nm in a fairly predictable pattern.
That naming convention started to drift in the mid-2010s. Chipmakers found ways to improve performance and density without shrinking every feature at the same rate, so the node number became more of a marketing label than a ruler measurement. A modern 3 nm chip might have a gate length around 3 nm but a metal half-pitch closer to 9 nm, depending on the manufacturer. To complicate things further, different companies measure and report nodes differently, which means “3 nm” from one manufacturer is not necessarily equivalent to “3 nm” from another.
What Actually Changes Between Nodes
Even though the name is no longer a precise measurement, moving to a new node still represents a real engineering leap. The core improvements are transistor density (more transistors fit on a chip of the same size), performance (transistors switch faster), and power efficiency (the chip draws less energy for the same work). These gains come from shrinking certain features, redesigning the transistor structure, using new materials, or some combination of all three.
The practical result is that a phone processor built on a 3 nm node can run faster and last longer on a battery charge than the same design built on a 5 nm node. For consumers, the node is essentially a shorthand for “how advanced is the manufacturing behind this chip.”
Transistor Architecture at Different Nodes
As transistors shrink, their physical structure has to change to keep working reliably. For most of semiconductor history, transistors were flat (planar), sitting on the chip surface like a pancake. At the 22 nm node, the industry shifted to a design called FinFET, where the channel that carries current sticks up like a thin fin. Wrapping the gate around three sides of that fin gave it much better control over the flow of electrons, which is critical when everything is so small that current can leak in unwanted directions.
FinFET technology has powered chips all the way down to 3 nm and remains the dominant architecture in high-volume production. But it’s reaching its physical limits. Below 3 nm, manufacturers are transitioning to gate-all-around (GAA) transistors, which stack thin sheets of material (nanosheets) and wrap the gate around all four sides. This gives even tighter control over current flow and reduces leakage further. Samsung has been pushing GAA at its 2 nm node, and TSMC’s upcoming 2 nm process uses the same approach. Below 2 nm, even GAA designs face serious challenges from quantum effects, where electrons begin tunneling through barriers that are supposed to block them.
Why Smaller Nodes Cost So Much More
The price of manufacturing a single silicon wafer rises dramatically at advanced nodes. Processing a 300 mm wafer at the 28 nm node costs roughly $3,000 at TSMC. At 3 nm, the same wafer costs around $19,500, more than six times as much. Samsung’s 3 nm wafers run about $15,000.
The biggest driver of that cost jump is the lithography equipment used to print patterns on the chip. At 7 nm and below, the industry switched from older deep-ultraviolet (DUV) light sources to extreme-ultraviolet (EUV) machines, which use a much shorter wavelength to draw finer lines. A single EUV tool costs over $150 million, and advanced nodes require more of these machines and more processing steps per wafer. That expense is why many chips, especially those that don’t need cutting-edge performance (car electronics, industrial controllers, Wi-Fi chips), are still manufactured on mature nodes like 28 nm or 16 nm where costs are far lower.
Physical Limits of Shrinking
There is a hard floor to how small transistors can get. As the gap between a transistor’s components drops to just a few nanometers, quantum tunneling becomes a serious problem: electrons pass through barriers they’re supposed to be blocked by, creating leakage current that wastes power and generates heat. Manufacturing at these scales also introduces defects and impurity issues that grow harder to control, because even a handful of misplaced atoms can change how a transistor behaves.
This is why the industry doesn’t rely on shrinking alone to improve chips. Advanced packaging techniques, which stack multiple chips vertically or connect them side by side on a single package, offer another path to better performance without requiring every transistor to be smaller. The node still matters, but it’s no longer the only lever chipmakers can pull.
Where the Major Chipmakers Stand
TSMC leads in advanced manufacturing, with its 3 nm process (N3) in high-volume production and its 2 nm node (N2) on the way. TSMC has also previewed a next-generation process called A14, which would push further into sub-2 nm territory. Samsung has moved aggressively into 2 nm with GAA transistors and continues investing in both leading-edge nodes and U.S.-based factories. Intel, which brands its nodes differently (its “Intel 18A” roughly competes with other companies’ 2 nm class), is also targeting advanced packaging as a differentiator alongside its foundry roadmap.
Because each company defines and names its nodes independently, direct comparisons require looking at actual transistor density and performance benchmarks rather than just the number on the label. A “3 nm” chip from one foundry may pack in more transistors per square millimeter than a “3 nm” chip from another.