CMOS, short for complementary metal-oxide-semiconductor, is the dominant technology used to build the chips inside nearly every electronic device you own. Your phone’s processor, your laptop’s memory, your camera’s image sensor: all built with CMOS. It works by pairing two types of transistors that complement each other, allowing circuits to use remarkably little power while packing billions of components onto a single chip.
How CMOS Circuits Work
Every CMOS circuit is built from two types of tiny switches called MOSFETs: one type (NMOS) conducts when turned on by a positive voltage, and the other (PMOS) conducts under the opposite condition. The key insight is pairing them together. Every NMOS transistor gets a matching PMOS partner, with their inputs and outputs wired together. When one switch is on, the other is off.
This complementary arrangement is what makes CMOS so efficient. At any given moment, only one transistor in each pair is actively conducting, which means almost no current flows through the circuit when it’s sitting in a stable state. Power is only consumed during the brief moment the transistors switch from one state to another. Older chip technologies like TTL kept current flowing constantly, which wasted energy and generated heat. CMOS largely eliminated that problem, which is why it became the standard for everything from wristwatches to supercomputers.
The PMOS transistors always connect to the power supply side of the circuit, while the NMOS transistors connect to the ground side. This strict arrangement prevents any direct path between power and ground in a stable state, keeping power consumption minimal.
Why CMOS Became the Standard
Low power consumption is the headline advantage, but it’s not the only one. CMOS circuits also resist electrical noise well. Because the paired transistors swing outputs cleanly between full voltage and zero, the signals are less likely to be corrupted by stray interference. This makes CMOS reliable even as circuits get smaller and signals get weaker.
CMOS also scales well. Shrinking transistors generally makes them faster and more power-efficient, and the complementary design holds up as dimensions decrease. That scalability allowed the semiconductor industry to follow Moore’s Law for decades, roughly doubling the number of transistors on a chip every two years. The combination of low power, high noise resistance, and excellent density made CMOS the foundation for virtually all modern digital electronics.
Where CMOS Technology Is Used
The most familiar applications are digital: microprocessors, microcontrollers, memory chips, and other logic circuits all rely on CMOS. But the technology extends well beyond computing.
CMOS image sensors are in nearly every camera made today, from smartphones to security systems to medical imaging equipment. These sensors convert light into electrical signals using the same basic transistor technology, with the added benefit that signal processing circuits can be built directly onto the same chip. Compared to older CCD sensors, CMOS imagers use as little as one-third the power (sometimes over 100 times less), operate at lower voltages, and allow high-speed image capture without visual artifacts like blooming and smearing. They also support random access to image data, meaning the chip can read out specific portions of an image rather than scanning the entire frame. CCDs still hold an edge in raw image quality for some specialized uses, particularly in low-noise and high-sensitivity applications, but CMOS sensors dominate the market because of their versatility, low cost, and ability to integrate processing on a single chip.
Beyond cameras, CMOS technology powers autonomous sensor systems, mixed-signal circuits that handle both analog and digital signals, biosensors, automotive electronics, and space instruments.
How CMOS Chips Are Manufactured
Building a CMOS chip involves repeating a core set of steps dozens or even hundreds of times on a thin disc of silicon called a wafer. The major steps are oxidation (growing an insulating layer on the silicon surface), lithography (projecting a microscopic pattern onto the wafer using light), ion implantation (injecting specific atoms into the silicon to change its electrical properties), etching (carving away material to transfer the pattern into the chip), and deposition (adding new layers of material).
Lithography is the step that defines the circuit’s features. The wafer is coated with a light-sensitive material called a resist. Light passes through a mask containing the circuit pattern, changing the resist’s chemical properties only where the light hits. A chemical bath then washes away either the exposed or unexposed resist, leaving a precise stencil on the surface. Through that stencil, engineers can etch trenches, implant atoms, or deposit new materials in exactly the right places. Once one layer is complete, the process starts again with a new mask for the next layer.
This cycle of lithography, implantation, etching, and deposition repeats to build up the complex three-dimensional structures that form transistors, wiring, and connections. A modern processor can require 80 or more lithography steps.
How Transistor Designs Have Evolved
For most of CMOS history, transistors were flat structures built on the surface of the silicon, called planar transistors. The gate (the part that switches the transistor on and off) sat on top of a flat channel. This worked well down to a point, but as transistors shrank below about 20 nanometers, the gate could no longer control the channel effectively. Current would leak through even when the transistor was supposed to be off.
The solution was the FinFET, introduced commercially at the 22-nanometer node. Instead of a flat channel, the silicon was shaped into a thin vertical fin, and the gate wrapped around it on three sides. This gave the gate two to three points of contact with the channel instead of just one, dramatically improving its ability to switch current on and off. FinFETs have been the workhorse transistor design for over a decade.
The latest evolution is the gate-all-around (GAA) architecture. Here, the channel is made from stacked horizontal nanosheets or nanowires, and the gate electrode completely surrounds each one on all four sides. This provides even tighter control than FinFETs and allows further shrinking. GAA transistors are now entering production at the most advanced manufacturing nodes.
Modern Manufacturing Nodes
Chip manufacturers measure their most advanced processes in nanometers, though the numbers are more of a marketing label than a literal measurement of any single feature. As of 2025, 2-nanometer nodes have just become available, with demand expected to soar 136 percent through 2030. The next target is 1.4-nanometer nodes, anticipated around 2027. Leading-edge wafers now cost $20,000 or more per wafer to produce, reflecting the extraordinary complexity of the equipment and processes involved.
To keep pushing performance at these tiny scales, chipmakers have replaced the traditional silicon dioxide gate insulator with materials that have a higher dielectric constant (often called “high-k” materials), paired with metal gate electrodes. This combination reduces electrical leakage that would otherwise waste power and generate heat. Researchers are also exploring channel materials beyond pure silicon, including germanium and compound semiconductors, to boost the speed at which current flows through transistors.
Physical Limits of Shrinking CMOS
CMOS scaling has progressed rapidly for more than three decades, but it faces hard physical limits. The primary challenge is power dissipation. As transistors get smaller, their insulating layers become so thin that electrons can quantum-tunnel straight through them, creating leakage current even when the transistor is off. Thermal excitation compounds the problem: random heat energy gives electrons enough of a kick to cross barriers they shouldn’t be able to cross.
These leakage currents add up. In a chip with billions of transistors, even a tiny leakage per transistor becomes significant total power drain. This static power consumption, the energy wasted when circuits aren’t actively switching, is now a major constraint on how far conventional CMOS can shrink. New transistor architectures like GAA help by improving gate control, but the fundamental physics of quantum tunneling sets a floor on how thin insulating barriers can get before they stop insulating. The industry continues to find engineering workarounds, but each generation requires increasingly creative solutions to keep performance improving.