Dennard scaling is the principle that as transistors shrink, their power density stays constant, meaning both voltage and current scale downward in proportion to size. First described by IBM engineer Robert Dennard and colleagues in their 1974 paper “Design of Ion-implanted MOSFETs with Very Small Physical Dimensions,” this principle served as a roadmap for the semiconductor industry for roughly 30 years. It explained why each new generation of chips could be faster, more efficient, and pack more transistors without overheating.
How Dennard Scaling Works
The core idea is called constant-field scaling. When you shrink every dimension of a transistor by some factor (call it S), you also reduce the operating voltage by the same factor. This keeps the electric field inside the transistor unchanged, which is important for reliability. The consequences ripple through every performance metric in a way that made chip designers very happy for decades.
If you shrink transistor dimensions by a factor of S, you can fit S² times as many transistors in the same chip area. Those smaller transistors also switch S times faster. Meanwhile, each individual transistor uses S² less power, which exactly offsets the higher density. The result: power density stays flat. You get a chip that’s dramatically more capable without drawing more power or producing more heat per square millimeter.
The combined effect was enormous. Each generation’s computational capability increased by a factor of S³: S² from the extra transistors and another S from the higher speed. This is why processor performance seemed to improve almost magically every couple of years during the 1980s and 1990s. The energy-efficiency gains came from two sources: shrinking the internal capacitance of each transistor (contributing a factor of S) and lowering the operating voltage (contributing another S²).
Dennard Scaling vs. Moore’s Law
These two concepts are often confused, but they describe different things. Moore’s Law is an observation about transistor count: the number of transistors on a chip roughly doubles every two years. Dennard scaling is about what happens to power and performance as those transistors shrink. Moore’s Law tells you how many transistors you’ll have. Dennard scaling told you that you could actually use all of them without melting the chip.
When both held true simultaneously, the effect was transformative. Chips got denser (Moore’s Law), faster, and stayed within the same power budget (Dennard scaling). This combination drove the era of rapidly increasing clock speeds, from tens of megahertz in the late 1980s to several gigahertz by the mid-2000s.
Why It Stopped Working
Dennard’s original model ignored two things that become significant at very small scales: leakage current and the threshold voltage needed to switch a transistor on and off. At larger transistor sizes, leakage was negligible. But after 30 years of shrinking, transistors became so small that current began leaking through even when they were supposed to be off. By Intel’s 65 nm process generation in 2005, gate insulating layers had thinned to just 1.2 nanometers, roughly five silicon atoms thick. That’s essentially the physical limit for the material being used, and at that thickness, electrons tunnel straight through.
The threshold voltage hit a similar wall. It had been scaled down alongside everything else for decades, but at very low levels, the leakage when a transistor is “off” increased by roughly a thousand-fold compared to earlier generations. Because of these leakage constraints, voltage couldn’t keep dropping, which broke the central bargain of Dennard scaling. Power density stopped staying constant. It started climbing.
This created what’s sometimes called the “power wall.” Since around 2006, practical processor clock speeds have been stuck near 4 GHz. Not because chip designers can’t build faster-switching transistors, but because running them faster would produce more heat than can be removed.
The Rise of Multicore and Dark Silicon
The chip industry’s initial response was to go wide instead of fast. Rather than pushing a single processor core to higher clock speeds, manufacturers put multiple cores on one chip. This let performance keep improving for workloads that could be split into parallel tasks, and it kept the economics of building smaller transistors viable for a while longer.
But multicore scaling ran into its own version of the same problem. A 2011 study from the University of California, San Diego projected that at 22 nm, roughly 21% of a chip’s transistors would need to be powered off at any given time just to stay within thermal limits. At 8 nm, that figure climbs above 50%. The transistors are there, but you can’t turn them all on at once. This phenomenon is called “dark silicon,” and it represents a fundamental gap between how many transistors Moore’s Law lets you build and how many you can actually use simultaneously.
The broader consequence is a divergence that defines modern chip design: transistor density keeps increasing, but energy-efficiency gains at the device level no longer keep pace. Each new process generation still delivers more transistors, but a shrinking fraction of the potential performance improvement can be realized within a fixed power budget.
How the Industry Adapted
With general-purpose clock speed gains largely exhausted, the industry shifted toward specialized hardware. Instead of building one fast processor that handles everything, modern chips dedicate different areas of silicon to specific tasks. Graphics processing units, machine learning accelerators, video encoders, and other specialized blocks can perform their particular job far more efficiently than a general-purpose core. This approach makes better use of available transistors by running only the circuits needed for a given workload and leaving the rest idle.
Chip architects have also introduced new transistor structures (like three-dimensional fin-shaped transistors) and new materials to wring out efficiency gains that Dennard’s original framework no longer provides. These innovations help, but they deliver incremental improvements rather than the exponential, predictable gains that Dennard scaling once guaranteed. The era when each new chip generation was automatically faster, denser, and the same power is over. Modern performance gains require increasingly clever engineering at every level, from the transistor to the software.