Etching in semiconductor manufacturing is the process of selectively removing layers of material from a silicon wafer’s surface to create the tiny structures that make up transistors, memory cells, and interconnects. It’s one of the core steps in building a chip: after a circuit pattern is printed onto the wafer using light (photolithography), etching carves that pattern into the actual material underneath. Every modern processor or memory chip goes through dozens of etching steps during production.
How Etching Fits Into Chip Fabrication
A semiconductor chip is built layer by layer. Each layer starts as a flat film of material deposited across the entire wafer. To turn that uniform film into useful circuit features, manufacturers first coat it with a light-sensitive material called photoresist, expose the resist to patterned light, and develop it so only certain areas remain covered. The exposed areas are then etched away, transferring the design from the mask into the material itself. After etching, the remaining photoresist is stripped off, and the process repeats for the next layer.
This means etching is the step that physically creates the features on a chip. Without it, every layer would remain a featureless blanket of material. The pattern on the mask is just a blueprint; etching is what turns it into actual gates, trenches, contact holes, and wiring channels.
Wet Etching: The Chemical Approach
Wet etching uses liquid chemicals to dissolve material. It was the only etching method available during the early days of chip development, and it’s still used today for certain steps where extreme precision isn’t required. The wafer is dipped into (or sprayed with) a chemical solution that reacts with the target material and carries it away.
Different materials require different chemicals. To etch silicon, manufacturers typically use potassium hydroxide (KOH) or similar alkaline solutions. To etch silicon dioxide (the insulating glass layer that appears throughout a chip), a mixture containing hydrofluoric acid is standard. In each case, a protective mask material sits on top of the areas you want to keep. Silicon dioxide, for instance, resists KOH very well, so it works as a mask when you’re etching the silicon underneath.
The main limitation of wet etching is directionality. Liquid chemicals attack material in all directions equally, a behavior called isotropic etching. This means the chemical eats sideways under the mask at the same rate it eats downward, producing rounded cavities and making features slightly larger than the mask intended. For older, larger chip designs this was acceptable. For modern chips with features measured in nanometers, that sideways undercutting is a dealbreaker. Wet etching is still chosen in situations where its excellent selectivity (the ability to remove one material without touching another) outweighs the need for tight dimensional control.
Dry Etching: Plasma-Based Precision
Dry etching replaced wet etching as the primary method for defining fine features. Instead of liquid chemicals, it uses reactive gases energized into a plasma, a state where the gas molecules are broken apart into charged ions and reactive neutral particles. The most common form is reactive ion etching (RIE).
In an RIE system, the wafer sits on an electrode inside a vacuum chamber. Reactive gases are fed in, and radiofrequency power (typically at 13.56 MHz) ionizes them into plasma. The positively charged ions accelerate toward the wafer and strike the surface with directional energy, while neutral reactive species also participate in the chemical removal. This combination of physical bombardment and chemical reaction is what gives dry etching its key advantage: anisotropy, meaning it etches preferentially downward rather than sideways.
Because the ions travel in a straight line toward the wafer, dry etching can produce nearly vertical sidewalls. That allows much finer feature sizes, down to several nanometers (limited mainly by the lithography mask), and high aspect ratios exceeding 10:1, where a hole or trench is more than ten times deeper than it is wide.
Selectivity and Uniformity
Two metrics define how well an etch process performs. The first is selectivity: the ratio of how fast the process removes the target material versus how fast it removes the mask or underlying layers. If your etch removes the target ten times faster than the mask, you have a selectivity of 10:1. Higher selectivity means you can etch deeper without destroying your mask or damaging layers you need to keep. Engineers tune gas chemistry to maximize this ratio. In one example, adding a small amount of a fluorine-containing gas to a chlorine-based plasma increased the selectivity of target material over photoresist by 4 to 8 times, because the additive simultaneously boosted the target etch rate and deposited a protective polymer on the resist.
The second metric is uniformity: how consistent the etch rate is across the entire wafer and from one wafer to the next. A 300mm wafer might have hundreds of individual chips on it, and the etch depth at the center needs to match the etch depth at the edges. Uniformity is tracked by measuring etch rates at multiple points across the wafer and calculating how much they deviate from the average. Poor uniformity means some chips on the wafer will have features that are too shallow or too deep, reducing yield.
High Aspect Ratio Etching
Modern 3D NAND flash memory pushes etching to its physical limits. These chips stack dozens or even hundreds of memory layers vertically, then punch narrow contact holes through the entire stack to connect them. The result is an extreme geometry problem: holes only about 100 nanometers in diameter that need to penetrate more than 2,000 nanometers of material. That’s an aspect ratio above 20:1.
At these dimensions, conventional plasma etching starts to introduce defects. The sidewalls of deep holes can bow outward, twist, or develop vertical striations, all of which ruin the electrical connections. Controlling the etch profile in these structures is one of the most difficult challenges in chip manufacturing today, and it’s a major factor determining whether the next generation of memory chips can be built at all.
Atomic Layer Etching
To handle the precision demands of the smallest and most delicate features, the industry has developed atomic layer etching (ALE). Instead of running continuously, ALE breaks the process into two alternating steps. First, a thin layer of reactive gas molecules attaches to the surface and chemically modifies just the top atomic layer of material. Then a separate energy pulse (often a burst of ions) removes only that modified layer. Because each step is self-limiting, meaning it naturally stops after processing one atomic layer, ALE provides control at the angstrom level (tenths of a nanometer).
This precision matters because at nanoscale dimensions, even a tiny overshoot in etch depth can destroy a feature. Conventional plasma etching lacks this level of controllability. ALE also causes less damage to the underlying substrate, which is critical for the thin, fragile structures in advanced logic and memory chips.
Environmental Considerations
The gases used in plasma etching are potent greenhouse gases. Fluorinated compounds like CF4, C2F6, SF6, and NF3 are standard in etch chambers because of their reactivity with silicon and its compounds, but they have extremely high global warming potentials, in some cases thousands of times greater than carbon dioxide, and they persist in the atmosphere for very long periods.
The semiconductor industry has been working to reduce these emissions through several approaches: optimizing processes so less gas is consumed per wafer, switching to alternative gases that are used more efficiently (so less escapes into the exhaust), and installing destruction systems that break down fluorinated gases before they reach the atmosphere. The U.S. EPA has partnered with the industry on these efforts, and companies have implemented combinations of all three strategies across their fabrication facilities.