Latchup is a failure condition in CMOS circuits where a parasitic structure accidentally turns on, creating a short circuit between the power supply and ground. Once triggered, the circuit locks into a high-current state that persists even after the triggering event is gone. If power isn’t cut quickly, the excessive current can overheat and permanently destroy the chip.
How Latchup Forms Inside a Chip
Every CMOS chip contains both p-type and n-type transistors built into layers of silicon. A side effect of this layered construction is that it inadvertently creates a four-layer structure (PNPN) that behaves like a thyristor, a type of electronic switch that latches on once activated. Specifically, the nested wells and diffusions in the silicon substrate form two parasitic bipolar transistors that share a collector junction. Under normal operation, these parasitic devices sit idle and do nothing.
The problem starts when something injects enough current or voltage to wake one of these parasitic transistors up. Once active, it feeds current into the second parasitic transistor, which amplifies it and feeds it right back to the first. This creates a positive feedback loop: each transistor drives the other harder, and both slam into a saturated, fully-on state within nanoseconds. The result is a low-resistance path directly between the power rail and ground, essentially a short circuit running through the chip’s own silicon.
For this runaway feedback to sustain itself, the combined current gain of the two parasitic transistors must exceed a value of one. Below that threshold, any injected current fizzles out. Above it, the loop is self-reinforcing and the latchup state persists indefinitely until power is removed.
What Triggers Latchup
Several events can inject enough energy to kick-start the parasitic feedback loop:
- Voltage spikes on input or output pins. If a signal overshoots above the supply voltage or undershoots below ground, even briefly, it can forward-bias junctions in the parasitic structure and inject minority carriers into the substrate.
- Power supply transients. Sudden glitches or noise on the supply rail can momentarily shift internal voltages enough to activate the parasitic path.
- Ionizing radiation. A single heavy ion striking the drain of a transistor can deposit enough charge to trigger latchup. Research on CMOS devices shows that once the energy transfer rate of the incoming particle exceeds about 6 MeV·cm²/mg, latchup occurs. This is a major concern for electronics in space, aircraft, and particle physics experiments.
- Elevated temperature. Heat makes the parasitic transistors more effective. Studies show that as chip temperature rises toward 450 K (about 177°C), the voltage needed to sustain latchup drops significantly, from levels safely above the supply voltage down to the supply voltage itself. This means a chip that’s latchup-free at room temperature can become vulnerable when it runs hot.
Why Latchup Is Destructive
During latchup, current flows through a path that was never designed to carry it. The silicon in that region heats rapidly. Because hotter silicon conducts even more current (a positive thermal feedback), the situation escalates: more current means more heat, which means more current. This thermal runaway can push localized temperatures past 650°C near the junction, hot enough to melt metal interconnects and permanently damage the transistor structures. Destruction can happen in as little as 250 microseconds after the event if power isn’t cut.
Even when latchup doesn’t immediately destroy the chip, it disrupts normal circuit operation. The power supply voltage sags because so much current is being diverted through the parasitic path, and logic states throughout the chip can become corrupted. The chip is effectively non-functional for as long as the latchup persists.
Latchup in Modern FinFET Chips
As transistors have shrunk to 7 nm and below, chip designers moved from traditional flat (planar) transistors to FinFET structures, where the transistor channel wraps around a thin fin of silicon. You might expect that smaller, more tightly controlled transistors would be less vulnerable to latchup, but the opposite has been observed. Testing of 7 nm bulk FinFET technology with high-energy proton and neutron beams revealed increased sensitivity to single-event latchup compared to older nodes. The tighter spacing between transistors means the parasitic structures are physically closer together, making the feedback loop easier to establish.
Design Techniques That Prevent Latchup
Chip designers use several layout strategies to break the parasitic feedback loop before it can form. The most common approach is placing guard rings, which are rings of heavily doped silicon that surround vulnerable transistors and intercept the minority carriers that would otherwise reach the parasitic structure. There are over 25 variations of guard ring design, broadly split into two categories: majority carrier guards that clamp substrate or well voltages, and minority carrier guards that collect stray charge before it can reach the parasitic transistors.
Placement matters as much as the type of guard. Guards can be positioned in the substrate near the source of injected current, surrounding the emitter of a parasitic transistor, at the edge of a well boundary, or inside the well itself. The choice depends on the specific circuit layout and the expected trigger source. Getting this right is a significant part of physical design, and less experienced designers rely on established layout rules to make these decisions.
Beyond guard rings, increasing the spacing between n-type and p-type transistors reduces the gain of the parasitic bipolar devices, pushing their combined gain below the critical threshold of one. This trades chip area for reliability.
Silicon-on-Insulator: Eliminating the Problem
The most effective solution is to eliminate the parasitic path entirely. Silicon-on-Insulator (SOI) technology does this by building transistors on a thin layer of silicon that sits on top of a buried oxide layer. This oxide physically isolates each transistor from the bulk substrate, severing the PNPN path that latchup requires. Individual transistor islands can be further separated by etching trenches down to the oxide layer, creating complete electrical isolation at geometries as small as lithography allows. SOI chips are inherently immune to latchup, which is one reason the technology is favored for space, military, and high-reliability applications.
Detecting and Recovering From Latchup
For systems that can’t use latchup-immune technology, real-time detection and fast power cycling is the main defense. The standard approach is to monitor current on every power supply rail. When current spikes above a set threshold, the system cuts power to the affected chip. NASA’s Jet Propulsion Laboratory uses detection circuits that can shut down power within about 100 milliseconds of detecting a high-current condition, fast enough to prevent thermal destruction in most cases.
This sounds straightforward, but it’s harder than it appears. Complex chips have many different internal power supply paths, and latchup can occur along any of them. The current drawn during latchup varies widely depending on which parasitic path activates. Setting detection thresholds is tricky because normal operating current fluctuates with workload and can vary between individual chips. You need to monitor all supply rails simultaneously and account for these variations to avoid both false alarms and missed events. After power is cycled, the chip typically resumes normal operation since latchup doesn’t cause permanent damage as long as power is cut quickly enough.