Static timing analysis (STA) is a method for verifying that all signals in a digital chip arrive at the right place within the right time window, without actually simulating the circuit’s logical behavior. Instead of feeding test inputs into a design and watching what happens (dynamic simulation), STA mathematically calculates the delay along every possible path through the circuit and checks whether timing requirements are met. This makes it both faster and more thorough than simulation, since it examines all paths rather than only those exercised by a specific set of test inputs.
STA is the industry-standard approach for timing verification, or “sign-off,” before a chip design is sent to a foundry for manufacturing. If any path has negative slack, meaning data arrives too late or too early, the design fails timing and cannot be fabricated.
How STA Differs From Dynamic Simulation
Dynamic simulation determines the full behavior of a circuit by applying a set of input stimulus vectors and observing outputs over time. It’s accurate for functional verification, but it can only check the timing of paths that those specific inputs actually activate. In a chip with millions of paths, covering them all through simulation is impractical.
STA sidesteps this problem entirely. It doesn’t care about logic values or input patterns. It simply traces every route a signal could take from start to finish, adds up the delays, and compares the result against timing constraints. This exhaustive coverage is why STA became the dominant method for timing closure in modern chip design.
Types of Timing Paths
STA categorizes every route a signal can take through a chip. The three main data path types are:
- Input to sequential element: A signal enters the chip through an input port and arrives at a flip-flop or register.
- Sequential element to sequential element: A signal leaves one register, passes through combinational logic, and arrives at the next register. This is the most common path type in synchronous designs.
- Sequential element to output: A signal leaves a register and travels to an output port of the chip.
Beyond data paths, STA also examines clock paths (from the clock source to each register’s clock pin) and asynchronous paths (from inputs to asynchronous set or clear pins on registers). Each type has its own timing requirements.
Setup Time, Hold Time, and Slack
The two fundamental checks in STA are the setup check and the hold check. Setup time is the minimum amount of time data must be stable before the clock edge arrives at a register. Hold time is the minimum amount of time data must remain stable after the clock edge. Violating either one means the register could capture the wrong value.
STA expresses whether these constraints are met using a value called slack. Positive slack means the timing requirement is satisfied with room to spare. Zero slack means the signal arrives exactly at the limit. Negative slack means a violation.
For setup checks, the formula is:
Slack = path requirement − maximum data delay + clock skew − clock uncertainty − setup time
For hold checks:
Slack = hold requirement + minimum data delay − clock skew − clock uncertainty − hold time
Clock skew in these formulas is the difference between the clock arrival time at the destination register and the source register. Skew can help or hurt depending on its direction: positive skew (where the clock arrives later at the destination) actually gives setup timing more room, but it tightens the hold margin. Clock uncertainty, which accounts for jitter and other variations, always reduces the available margin for both checks.
What Clock Skew and Jitter Do to Timing
Clock skew is a spatial variation: different registers on the chip receive the clock edge at slightly different times because of differences in wire length and buffering along the clock distribution network. It’s partly predictable and partly random.
Jitter is a temporal variation: consecutive clock edges at the same register don’t arrive at perfectly regular intervals. Noise, power supply fluctuations, and other factors cause small cycle-to-cycle deviations. Unlike skew, jitter always degrades performance because it eats into timing margins on both sides of the clock edge.
Together, skew and jitter reduce the effective clock cycle available for useful logic. The design’s maximum operating frequency depends on keeping enough margin after accounting for both. In simplified terms, the clock period minus twice the jitter must be greater than the sum of register overhead, logic delay, and setup time.
Inputs an STA Tool Needs
Running STA requires several files that together describe the chip’s structure, timing behavior, and design intent:
- Gate-level netlist: A text description of every standard cell in the design and how they’re connected. This is the structural blueprint of the chip.
- Timing library (.lib): Contains the timing, area, and power characteristics of each standard cell type under different operating conditions (variations in process, voltage, and temperature). Delay models within this library, such as non-linear delay models, allow the tool to calculate how fast each gate switches for a given input transition and output load.
- SDC (Synopsys Design Constraints): Defines the timing intent, including clock definitions, clock frequencies, input and output delay requirements, and timing exceptions. This file tells the tool what “correct” timing looks like.
- Parasitic data (SPEF): Captures the resistance, capacitance, and inductance of every wire and via in the design. These parasitics slow signals down, and accurate parasitic data is critical for realistic delay calculations, especially at advanced process nodes where wire delay can dominate gate delay.
- Physical layout data (DEF): Contains placement information for cells, macros, routing, and pin locations. This gives the tool the physical context needed to correlate with parasitic data.
How Delays Are Calculated
Total path delay is the sum of gate delays and interconnect (wire) delays along a path. Gate delays come from the timing library, which maps input signal slope and output capacitive load to a delay value using lookup tables or current-source models.
Wire delays are trickier because real interconnects behave as distributed networks of resistance and capacitance. The simplest analytical model, called Elmore delay, estimates wire delay from the first moment of the circuit’s impulse response. It works well for simple nets but can be inaccurate when there’s significant resistive shielding. More advanced models use two circuit moments for better accuracy, and some tools use logarithmic or statistical fitting to match real waveform behavior more closely.
Signal slew, the time it takes a signal to transition from low to high or vice versa, is calculated alongside delay because a slow-rising signal at one gate’s output becomes a slow-arriving input at the next gate, compounding delay through the path. Accurate slew propagation is essential for realistic timing results.
Timing Exceptions
Not every path in a design needs to meet single-cycle timing. STA tools allow designers to declare exceptions that override default constraints:
A false path is a route that exists structurally in the netlist but can never be activated during normal operation. For example, two multiplexer select signals might be mutually exclusive, making certain combinations of paths physically impossible. Declaring these as false paths prevents the tool from wasting effort optimizing paths that don’t matter.
A multicycle path is one where the design intentionally allows data more than one clock cycle to propagate. This is common when a slow operation feeds into a register that’s only sampled every second or third cycle. Without this exception, STA would flag these paths as setup violations even though the design functions correctly.
Getting exceptions right is important. Missing a real timing path by incorrectly marking it as false can cause silicon failures that are extremely difficult to debug after fabrication.
Timing Sign-Off and Closure
Before a chip design goes to the foundry, it must pass timing sign-off: every path in the design must show zero negative slack across all required operating conditions. These conditions, called corners, represent combinations of process variation, voltage, and temperature that the chip might encounter in real use. The slowest corner (high temperature, low voltage, worst-case transistors) is typically the hardest to pass for setup checks, while the fastest corner (low temperature, high voltage, best-case transistors) is the critical one for hold checks.
If timing is clean at these critical corners, other corners generally satisfy timing within about 5% variation. The industry’s gold-standard sign-off tool is Synopsys PrimeTime, which provides the trusted reference for timing, signal integrity, and power analysis that foundries and design teams rely on for first-pass silicon success.
Timing closure, the iterative process of fixing violations until all slack is non-negative, often consumes a large portion of the overall chip design schedule. Engineers may resize gates, add buffers, restructure logic, adjust placement, or reroute wires to fix failing paths. Each change requires re-running STA to confirm the fix didn’t introduce new violations elsewhere.