V-NAND (Vertical NAND) is a type of flash memory that stacks storage cells on top of each other in layers, rather than shrinking them side by side on a flat surface. This vertical approach lets manufacturers fit far more storage into the same physical space. Samsung coined the term “V-NAND” when it pioneered the technology, though the broader industry calls the same concept “3D NAND.” If you’ve bought an SSD in the last several years, it almost certainly uses this technology.
How V-NAND Differs From Traditional Flash
Traditional NAND flash, sometimes called planar or 2D NAND, arranges memory cells in a single flat layer on a silicon wafer. For years, manufacturers made these cells smaller and smaller to increase storage density. But by the mid-2010s, cells had shrunk so much that they started interfering with each other electrically, causing data errors and reducing the lifespan of the drive.
V-NAND solved this by going vertical. Instead of making cells tinier, engineers stack dozens or even hundreds of layers of memory cells into a tall column. Think of it like building a high-rise apartment building instead of sprawling a neighborhood across more land. Each cell can actually be larger than those in late-generation planar NAND, which improves reliability while still packing in more total storage per chip.
The Physical Structure Inside a V-NAND Chip
A V-NAND chip starts with alternating thin films of metal and silicon dioxide stacked on top of each other. These layers form the word lines, which are essentially the control gates that read and write data to individual cells. Once the stack is built, vertical holes are drilled through the entire structure using plasma etching. Each hole becomes a “channel” lined with a thin cylinder of polysilicon, creating what engineers call a macaroni channel structure (because the channel is hollow in the center, like a tube of pasta).
Each point where a channel hole intersects a word line becomes a memory cell. So a single vertical hole passing through 128 layers creates 128 cells in a tiny column. Multiply that across billions of channel holes and you get enormous storage density in a chip roughly the size of a fingernail.
Charge Trap Flash: How Data Is Actually Stored
Most planar NAND used a structure called a floating gate to store data. Electrons were trapped in a small conductive pocket, and the presence or absence of those electrons represented a 1 or a 0. This worked well in two dimensions but became difficult to manufacture reliably in vertical stacks.
V-NAND instead uses charge trap flash (CTF) technology. Rather than storing electrons in a conductive pocket, CTF traps them in an insulating layer with tiny, isolated pockets scattered throughout. The practical benefit is significant: if a small defect develops in the insulating barrier around a floating gate, all the stored charge can leak out and the data is lost. With charge trap flash, a similar defect only drains the few electrons right next to the leak. The rest stay put. This makes V-NAND inherently more resistant to data loss.
CTF also consumes less power and allows faster read and write operations compared to floating gate designs. These advantages become more important as layer counts increase, because taller stacks demand tighter tolerances and more efficient operation at every level.
Why Cell-to-Cell Interference Matters Less
One of the biggest problems with shrinking planar NAND was that neighboring cells would electrically interfere with each other. Charge stored in one cell could subtly shift the readings of the cell next to it, leading to data corruption. Engineers developed complex error correction to compensate, but the problem worsened with each generation.
Vertical stacking eases this problem because the cells can be physically larger and more spread out than in the most aggressively shrunk planar designs. Researchers have also developed structural modifications to further reduce interference, including inserting oxide barriers or grounding layers between cells to block stray electric fields from affecting neighboring storage sites. These techniques have proven effective in both crystalline and polysilicon channel structures.
Layer Counts Keep Climbing
The first commercial V-NAND from Samsung in 2013 had 24 layers. Each subsequent generation roughly doubled the count. By 2020, 128-layer chips were common. Samsung’s 9th-generation V-NAND, which entered mass production recently, uses the highest layer count in the industry through a double-stack approach, where two shorter stacks are built and connected rather than etching a single impossibly tall column. Other manufacturers like Micron, SK Hynix, and Kioxia have pushed past 200 layers with similar techniques.
More layers means more storage per chip, which translates directly into higher-capacity drives at lower cost. The channel hole etching process is one of the most technically challenging steps in manufacturing, because drilling a perfectly straight, narrow hole through hundreds of layers without it tapering or deforming is extraordinarily difficult. Slight imperfections near the bottom of the hole can create non-circular channels that degrade electrical uniformity across cells, so precision here is a key differentiator between manufacturers.
What This Means for SSDs You Can Buy
V-NAND is the technology inside virtually every modern consumer SSD, whether it connects through SATA or the faster NVMe/PCIe interface. As of 2024, mainstream SSDs using QLC (quad-level cell) V-NAND commonly offer 2 TB of storage on a single drive, with 4 TB options widely available and 8 TB consumer drives starting to appear, though at premium prices.
The per-terabyte cost for consumer NVMe drives has settled around $100 per TB for PCIe 4.0 and 5.0 models. SATA-based V-NAND drives tend to be cheaper but are limited in speed by the older interface. The continued increase in V-NAND layer counts is expected to push capacities higher and prices lower over the next several years, as each generation fits more storage onto the same number of silicon wafers.
When shopping for an SSD, you’ll see terms like TLC (triple-level cell) and QLC (quad-level cell) alongside V-NAND or 3D NAND branding. These refer to how many bits each cell stores: TLC stores three bits per cell and offers better endurance, while QLC stores four bits and maximizes capacity at the cost of slightly fewer write cycles. Both rely on the same vertical stacking technology underneath.