Wafer fabrication is the process of building integrated circuits (microchips) on thin discs of silicon, layer by layer, through hundreds of precisely controlled chemical and physical steps. Every processor in your phone, laptop, car, and countless other devices starts as a blank silicon wafer and emerges from a fabrication facility, or “fab,” with billions of transistors etched into its surface. The entire process can take two to three months from start to finish and requires some of the most controlled environments on Earth.
How Silicon Wafers Are Made
Everything begins with ultra-pure silicon. Sand is refined into a polycrystalline silicon feedstock, then melted at 1,414°C in a crucible. A small seed crystal is dipped into the molten silicon and slowly pulled upward while rotating. This is called the Czochralski process, and it produces a single cylindrical ingot of monocrystalline silicon, sometimes weighing over 100 kilograms. The temperature gradient along the growing crystal is tightly managed, dropping from around 1,407°C at the contact surface to much cooler temperatures further up, which controls how atoms arrange themselves into a perfect, defect-free lattice.
Once the ingot is grown, it’s sliced into wafers less than a millimeter thick using diamond-coated wire saws. These wafers are then polished to an almost perfectly flat mirror finish. Modern fabs typically use 300mm (about 12-inch) diameter wafers, and each one will eventually yield hundreds of individual chips.
The Cleanroom Environment
A single dust particle landing on a wafer can ruin a chip. To prevent that, wafer fabrication takes place inside cleanrooms classified under ISO standards based on the number of airborne particles allowed per cubic meter of air. Advanced semiconductor fabs operate at ISO Class 1 or Class 2, the most stringent levels. An ISO Class 1 cleanroom permits no more than 10 particles of 0.1 micrometers or larger per cubic meter. For comparison, the outdoor air you’re breathing right now contains millions of particles per cubic meter at that size.
Workers in these environments wear full-body “bunny suits” that cover skin and hair completely. Air is continuously filtered, temperature and humidity are held within narrow ranges, and even vibrations from nearby traffic can be a concern.
Printing Patterns With Light
The core of wafer fabrication is photolithography, the process of using light to transfer circuit patterns onto the silicon surface. A wafer is coated with a light-sensitive material called photoresist, then exposed to light shining through a patterned mask. Where the light hits, the photoresist changes chemically and can be washed away, leaving behind a precise pattern that guides the next processing step.
The size of features you can print depends on the wavelength of light. Older deep ultraviolet (DUV) systems use krypton-fluoride lasers at 248 nanometers, capable of printing features down to about 80nm. More advanced DUV systems use argon-fluoride lasers at 193nm, pushing feature sizes to 38nm. The latest extreme ultraviolet (EUV) lithography uses light at just 13.5nm, more than 14 times shorter than DUV wavelengths. That jump in resolution is what makes today’s most advanced chips possible. A single EUV machine costs over $100 million and is built by only one company in the world.
Depositing and Growing Layers
Chips are three-dimensional structures. Transistors, wiring, and insulating layers are stacked on top of each other, and each layer must be deposited with extreme precision. Two major techniques handle this.
Chemical vapor deposition (CVD) introduces gases into a chamber, where they react on the wafer surface to form a solid film. CVD is well suited for building up thicker layers and is widely used to create the materials found in everything from integrated circuits to solar panels and LEDs.
Atomic layer deposition (ALD) works differently. It builds films one atomic layer at a time through self-limiting chemical reactions, meaning each cycle adds exactly one layer of atoms before stopping on its own. This gives engineers atomic-scale control over thickness, which is critical for the ultra-thin films (often below 100nm) that modern transistors require. ALD produces exceptionally uniform coatings that follow the contours of complex surface features, a property called conformity that becomes more important as chip designs grow more intricate.
Etching the Circuit
After a pattern is defined by photolithography and a new material has been deposited, unwanted material needs to be removed. This is etching, and it comes in two forms.
Wet etching uses acidic or alkaline chemical solutions to dissolve material through a chemical reaction. It’s straightforward, but it removes material equally in all directions, like water eroding a sandcastle from every side. This makes it difficult to carve the steep, narrow features that modern chips demand.
Dry etching solves this problem by using plasma, an energized gas in a vacuum chamber. High-energy particles smash into the wafer surface, removing material in a controlled, directional way. Because the plasma ions travel in a specific direction, dry etching can carve straight down into a surface without undercutting the pattern sideways. This directional, or anisotropic, etching is essential for producing the sharp vertical walls of today’s nanoscale transistors.
Doping: Tuning Electrical Properties
Pure silicon doesn’t conduct electricity well enough to function as a transistor. To make it work, engineers deliberately introduce tiny amounts of other elements (like boron or phosphorus) into specific regions of the wafer. This process is called doping, and it controls whether a region of silicon carries a positive or negative charge.
The primary method is ion implantation. Atoms of the desired element are ionized and accelerated toward the wafer at energies between 5 and 200 keV. The energy level determines how deep the atoms penetrate. A boron implant at 30 keV, for example, peaks at a depth of about 110nm below the surface, with a spread of roughly 38nm on either side. By adjusting the energy and dose, engineers can place dopant atoms exactly where they’re needed, defining the transistor’s electrical behavior with nanometer-level precision.
Smoothing the Surface
With dozens of layers being deposited and etched on top of each other, the wafer surface can become uneven. Even small height variations cause problems for photolithography, which needs a flat surface to focus properly. Chemical mechanical planarization (CMP) fixes this by pressing the wafer against a rotating pad with a chemical slurry. The combination of gentle abrasion and chemistry removes high spots while leaving low areas intact, flattening the surface to nanoscale or even angstrom-level smoothness. This step is repeated many times throughout the fabrication process, typically after each new layer is built up.
Testing and Dicing
Once all the layers are complete, every chip on the wafer is tested while still attached to the disc. Tiny probe needles contact each chip’s electrical pads and run functional tests. Chips that fail are marked and will be discarded later. After testing, the wafer is cut apart, or “diced,” into individual chips using a precision saw or laser. Working chips are then packaged into the protective housings you’d recognize if you’ve ever looked at the components on a circuit board.
Where the Industry Stands Now
The push to shrink transistors continues to drive wafer fabrication forward. TSMC, the world’s largest contract chipmaker, began volume production of its 2nm process node in the fourth quarter of 2025, with full ramp-up underway in 2026. Each new generation packs more transistors into the same area, improving performance and energy efficiency. The cost reflects the complexity: fabricating a single wafer at TSMC’s 3nm-class nodes runs roughly $25,000 to $27,000.
These prices help explain why only a handful of companies in the world can afford to build and operate leading-edge fabs. A modern fabrication facility costs $10 billion or more and takes years to construct. The equipment inside, the chemicals, the cleanroom infrastructure, and the engineering expertise all represent decades of accumulated technological progress, all aimed at the same goal: building circuits so small that individual features are just a few dozen atoms wide.