Wafer level packaging (WLP) is a method of packaging semiconductor chips while they are still part of the silicon wafer, rather than cutting them apart first and then packaging each one individually. This approach produces a final package that is essentially the same size as the chip itself, making it one of the smallest packaging options available. The WLP market was valued at roughly $10.86 billion in 2025 and is projected to reach $28.81 billion by 2035, driven largely by demand for compact electronics, AI processors, and high-performance computing.
Traditional chip packaging works like this: a wafer full of chips gets sliced into individual pieces (called “dies”), and each die is placed into a larger package with a protective shell and external connections. WLP flips that sequence. All the packaging steps, including adding connection points, protective layers, and rerouted wiring, happen while the chips are still together on the wafer. Only then are they separated. This is faster, cheaper per unit, and results in packages with better electrical performance because the signal paths are shorter.
Fan-In vs. Fan-Out Designs
WLP comes in two main flavors, and understanding the difference matters because they serve very different applications.
Fan-in WLP places all external connection points (solder balls) directly on the face of the chip. Since the connections have to fit within the chip’s footprint, this design works best for smaller chips with lower connection counts. A basic fan-in structure tops out at around 36 connections on a 3mm × 3mm chip using standard designs. More advanced structures, like those using copper posts, can push that to 144 connections on a 6mm × 6mm chip while still meeting reliability requirements during thermal cycling. You’ll find fan-in WLP in devices like power management chips, sensors, and RF components where the connection count stays modest.
Fan-out WLP was developed to break past those limits. Instead of confining connections to the chip’s surface area, fan-out designs embed the chip in a molded material and extend wiring outward beyond the chip’s edges. This allows a much higher number of connections without requiring a larger chip. Fan-out packages also deliver improved thermal and electrical performance compared to conventional packages. They can even integrate multiple chips and passive components into a single package, which makes them a key technology for advanced processors, 5G modems, and application processors in smartphones.
How Redistribution Layers Work
The redistribution layer (RDL) is the wiring system that makes WLP possible. Chips are designed with tiny connection pads arranged in positions that make sense for the circuit layout, but those positions rarely match where external solder balls need to go. The RDL reroutes electrical paths from the chip’s original pad locations to a new grid of connection points on the package surface.
RDLs are built from alternating layers of a polymer insulating material (typically polyimide) and copper wiring. Copper traces run horizontally to reroute signals, while vertical copper connections called vias link one layer to the next. As chips grow more complex, particularly for AI and high-performance computing, the number of signals that need routing increases dramatically. Modern RDLs respond by shrinking the width and spacing of copper traces, packing more connections into the same area. In the most advanced packages, RDLs enable communication between stacked memory and processors by providing the dense interconnect pathways those architectures require.
Under-Bump Metallization
Between each solder ball and the chip’s surface sits a thin stack of metal layers called under-bump metallization (UBM). This structure serves several critical functions. The bottom layer, typically made from materials like titanium-tungsten or chromium, bonds directly to the chip’s aluminum pad and acts as a diffusion barrier, preventing solder from migrating into the chip and damaging the circuitry. Above that, a wettable layer (usually copper or nickel) gives the molten solder something to grip during the reflow process when connections are formed.
Nickel is increasingly favored for this wettable layer because it reacts with solder more slowly than copper does, which improves long-term reliability. The UBM stack may only be a few micrometers thick total, but its composition directly determines how well the solder joints hold up over thousands of thermal cycles as a device heats up and cools down during normal use.
Electrical Performance Advantages
One of the biggest reasons WLP has gained traction is electrical performance. In traditional packaging, thin gold or copper wires connect the chip to the package frame. These wires act as tiny antennas and inductors, introducing parasitic inductance that degrades signal quality, especially at high frequencies. The longer and thinner the wire, the worse the problem.
WLP eliminates wire bonds entirely. Signals travel through short copper traces in the RDL and directly into solder bumps, cutting the electrical path length dramatically. Advanced interconnect structures designed to minimize parasitic effects can reduce parasitic inductance by more than 50% compared to conventional approaches. In practical terms, this means less voltage overshoot during switching, cleaner signal transitions, and lower switching energy losses, improvements that compound across billions of operations per second in modern processors.
Thermal Challenges at Small Scales
Packing more functionality into smaller packages creates a heat problem. With WLP, the chip itself is the package, so there’s no large metal lead frame or heat spreader to absorb and distribute thermal energy. As power densities climb, especially in fan-out designs integrating multiple chips, the packaging materials need to conduct heat efficiently.
Traditional molding compounds used in fan-out WLP are epoxy-based and not particularly good at conducting heat. Newer liquid molding compounds with high thermal conductivity are being developed, but they introduce their own complications. Loading these compounds with enough thermally conductive filler particles to be effective changes their flow behavior and can cause warpage, where the package bends or distorts due to mismatched expansion rates between materials. Managing this tradeoff between thermal performance and mechanical reliability is one of the defining engineering challenges in current WLP development.
3D Stacking and Chiplet Integration
WLP technology forms the foundation for the most advanced chip architectures in production today. In 2.5D integration, multiple chiplets (smaller, specialized chips) sit side by side on a shared interposer, a thin layer of silicon or organic material containing dense RDL wiring that connects them. This lets manufacturers combine chips built on different manufacturing processes into a single package, pairing a cutting-edge logic chip with memory or analog components made on older, cheaper processes.
True 3D integration goes further by stacking chips directly on top of each other. Intel’s Foveros technology, for example, bonds chips face-to-face using micro-bumps just 36 micrometers in diameter. A base logic chip on the bottom tier connects to memory or additional logic stacked above it through these tiny vertical links. This vertical approach offers denser interconnections and shorter signal paths than placing chips side by side, but it intensifies the thermal challenges since heat from the bottom chip has to pass through the one above it to escape.
These multi-chip architectures are what enable modern AI accelerators and high-end processors to deliver the performance they do. Rather than trying to build one enormous chip (which gets exponentially more expensive and harder to manufacture), designers break the system into smaller chiplets and reassemble them using WLP-derived packaging technologies. The packaging, in many ways, has become as important as the silicon itself.